1. Field of the Invention
The present invention relates to an oscillator generating an electrical oscillation signal and more particularly, to an oscillator capable of operating stably.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional oscillator. The oscillator is constituted by a current-controlled oscillation circuit 2, a phase-locked loop circuit (PLL) 4, a reference signal source 6, a low pass filter (LPF) 8 and an oscillation frequency control circuit 10.
The current-controlled oscillation circuit 2 is a differential ring oscillator having interpolating delay circuits interconnected in multi-stage in which the transfer time of a signal from an input terminal to an output terminal is variably controlled in response to a current outputted from the oscillation frequency control circuit 10.
The PLL 4 generates and outputs an oscillation frequency control voltage Vtune in response to a phase difference between an output oscillation signal Vout from the current-controlled oscillation circuit 2 and a reference signal from the reference signal source 6.
FIG. 2 is a circuit diagram schematically showing a conventional PLL 4. The PLL 4 is constituted by a phase comparator 12, a switch control circuit 14 and field effect transistors (FETs) 16, 18. The phase comparator 12 is inputted the output oscillation signal Vout and the reference signal S and then detects the phase difference between these signals. The switch control circuit 14 receives a comparison result signal from the phase comparator 12 and generates switch control signals which selectively turn on FETs 16, 18. The FET 16 is a FET of P channel connected between a power source of positive voltage Vcc and an output terminal of Vtune, and a switch control signal CP is applied to a gate thereof from the switch control circuit 14. Meanwhile, the FET 18 is a FET of N channel connected between a ground potential GND and an output terminal of Vtune, and the switch control signal CN is applied to a gate thereof from the switch control circuit 14. For example, in a period in which Vout is followed by the reference signal S in phase, CP becomes low (L) level and FET 16 becomes ON state. Accordingly, Vtune is increased. Meanwhile, in a period in which Vout is preceded by the reference signal S in phase, CN becomes high (H) level and FET 18 becomes ON state. Accordingly, Vtune is decreased.
FIG. 3 is a circuit diagram showing a conventional oscillation frequency control circuit 10. The oscillation frequency control circuit 10 is a differential amplifier circuit, and a current path consisting of channels of transistors Q1 and Q2 which are interconnected serially and a current path consisting of channels of transistors Q3 and Q4 which are interconnected serially are connected to a common constant current source I0. A base of Q1 is connected to a reference voltage Vc, and Vtune is applied to a base of Q3. The ratio of current Ib flowing through Q2 and current Ia flowing through Q4 out of currents supplied from the constant current source I0 is changed in response to the difference of Vtune and Vc which are differential input signals. Vc is set to a voltage corresponding to Vcc/2 which is intermediate voltage between Vcc and GND.
The current Ib flowing to Q2 and current Ia flowing to Q4 are supplied to the interpolating delay circuit constituting the current-controlled oscillation circuit 2 by using a current mirror circuit, respectively. For example, the current Ib becomes a current source of a differential amplifier circuit of low speed path of the interpolating delay circuit, and meanwhile, the current Ia becomes a current source of a differential amplifier circuit of high speed path of the interpolating delay circuit. As Vtune is decreased and Ia is increased, in the interpolating delay circuit, a signal transfer by the high speed path out of low speed path and high speed path parallelly connected becomes dominant, the time of the signal transfer is decreased, and thereby phase delay of Vout can be eliminated. Meanwhile, as Vtune is increased and Ib is increased, a signal transfer by the low speed path becomes dominant, the time of the signal transfer is increased, and thereby phase lead of Vout can be eliminated.
FIG. 4 is a graph showing the variation of the Ia and Ib of a conventional oscillation frequency control circuit 10 with respect to Vtune. A region in which Ia and Ib are not changed with respect to the variation of Vtune is referred to as a saturation region. Meanwhile, a region in which Ia and Ib are changed with respect to the variation of Vtune is referred to as a linear region. In the conventional oscillation frequency control circuit, the linear region is a relatively small range such as 0.1 V or less with a center on Vc, and an oscillation frequency of the current-controlled oscillation circuit 2 is changed in this linear region. However, the oscillation frequency is not changed in the saturation region other than the small linear region. By this characteristic, in one case, since the change of an oscillation frequency in accordance with the variation of Vtune in the linear region is steep, although Vtune is changed slightly by noise, the oscillation frequency is changed largely. That is, there has been a problem that a phase noise characteristic of the PLL is deteriorated. Also, in the other case, if Vtune is changed up to a saturation region, Ia and Ib become constant and thereby the oscillation frequency becomes to be not changed. That is, there has been a problem that the PLL becomes inability to control frequency (deadlock state).